1. Field of the Invention
The present invention relates to a technology for controlling power-supply timings for supplying powers to circuit elements of a plurality of power-supply lines in an image forming apparatus.
2. Description of the Related Art
In an image processing device for an image forming apparatus such as a copier, a facsimile (fax), a printer, a scanner, and a multifunction product (MFP), an output capacity and the number of output lines of a power source tends to increase with an improvement of image-processing performance. Particularly, the MFP includes a plurality of modules for controlling various functions each having a control circuit including a plurality of central processing units (CPUs). A power source of the MFP needs to supply predetermined powers to circuit elements of the modules, so that the capacity and the number of output levels of the power source are increased. Therefore, the MFP employs a power source including a plurality of output lines each of which outputs a power with the same level.
In a so-called power-saving mode, if no operation is performed on the MFP for a predetermined time after the power is turned on, the MFP shifts sequentially to a higher power-saving state from a standby mode, a preheating mode, a low-power mode, and to a sleep mode.
In an apparatus that has the power-saving mode and a plurality of power-supply lines, if power-on timings (power-supply timings) of the power-supply lines are not set in an appropriate order, a sneak current flows between semiconductor circuits, which affects lifetimes of semiconductor elements.
An image forming apparatus disclosed in Japanese Patent Application Laid-open No. 2004-266661 includes a timing generating unit to which a power is supplied while a main switch is on. A power to be supplied to mechanical units and function circuits constituting the image forming apparatus is divided into a plurality of power-supply lines. When the image forming apparatus is turned on, powers from the power-supply lines are supplied in a predetermined order of power-supply timings, and when the image forming apparatus changes a mode between power-saving states, a change of the mode is performed by controlling the order of power-supply timings.
In a conventional technology, the image forming apparatus includes a power source that is divided into a plurality of power-supply lines. The powers from the power-supply lines are supplied in a predetermined order of power-supply timings at the time of turning on the power, and a change of the mode between power-saving states is performed by controlling the order of the power-supply timings. Therefore, there is room for improvement for preventing the sneak current between semiconductor circuits more appropriately, so that the lifetimes of the semiconductor elements are maintained.
Specifically, in the conventional technology, the sneak current between the semiconductor circuits is prevented in the level of the whole apparatus by controlling the order of the power-supply timings; however, the sneak current occurs also in each of the power-supply lines in the image forming apparatus. For example, an image-data transfer circuit for transferring image data, which is a function circuit inside a power-supply line, uses a first power-saving mode power that is supplied even in the power-saving mode and a second power-saving mode power that is not supplied in the power-saving mode, the conventional technology cannot prevent the sneak current in the level of each power-supply line.
The image-data transfer circuit uses a first power generated from the first power-saving mode power and a second power generated from the second power-saving mode power supplied to the image-data transfer circuit at an output timing of the power supply unit (PSU), and the first power is controlled by a control signal from a controller, while the second power is generated irrespective of the control signal. Therefore, when the first power and the second power are supplied without considering the timing, and if the power-supply timings of the first power and the second power coincide or an interval between the power-supply timings is short, the second power may be generated before the first power, causing the sneak current between the semiconductor circuits (between the circuit elements).
In other words, although it is considered that the first power-saving mode power is generated and the second power-saving mode power is not generated in the power-saving mode, a case is still out of consideration in which the second power-saving mode power is generated and the first power-saving mode power is not generated. Therefore, a supply of the second power-saving mode power alone may cause the sneak current between the semiconductor circuits.
Moreover, because a power is typically applied from a lower voltage level, and application specific integrated circuits (ASICs) often have a specification in which a lower voltage is first supplied, no particular consideration needs to be given for power supply to the ASICs. However, some ASICs have a different specification in which a higher voltage is first supplied, which is not considered in the conventional technology. In the latter case, if a lower voltage is first supplied to the ASICs, the ASICs cannot fully satisfy the specification. In such case, although the ASICs usually operate in a normal condition, there still is a possibility of causing a malfunction, and the lifetimes of the ASICs may be shortened because of a heavy load imposed on the ASICs.